IDT82P2808 Datasheet, PDF (106/144 Pages) Integrated Device Technology – 8(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2808
8(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
INTS1 - Interrupt Status Register 1
Address: 021H, 061H, 0A1H, 0E1H, 121H, 161H, 1A1H, 1E1H, (CH1~CH8)
7E1H (CH0)
Type: Read / Write
Default Value: 00H
7
6
5
4
3
SAIS_IS
LAIS_IS
PA_IS
-
-
2
1
0
-
IBA_IS
IBD_IS
Bit
Name
Description
7
SAIS_IS This bit indicates the interrupt status of the SAIS.
0: No SAIS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: SAIS interrupt is generated and is reported by the INT pin. When the AIS_IES bit (b6, INTES,...) is ‘0’, a transition from ‘0’ to ‘1’
on the SAIS_S bit (b7, STAT1,...) set this bit to ‘1’; when the AIS_IES bit (b6, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or from
‘1’ to ‘0’) on the SAIS_S bit (b7, STAT1,...) set this bit to ‘1’.
6
LAIS_IS This bit indicates the interrupt status of the LAIS.
0: No LAIS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: LAIS interrupt is generated and is reported by the INT pin. When the AIS_IES bit (b6, INTES,...) is ‘0’, a transition from ‘0’ to ‘1’
on the LAIS_S bit (b6, STAT1,...) set this bit to ‘1’; when the AIS_IES bit (b6, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or from
‘1’ to ‘0’) on the LAIS_S bit (b6, STAT1,...) set this bit to ‘1’.
5
PA_IS This bit indicates the interrupt status of the PRBS/ARB pattern synchronization.
0: No PRBS/ARB pattern synchronization interrupt is generated; or a ‘1’ is written to this bit. (default)
1: PRBS/ARB pattern synchronization interrupt is generated and is reported by the INT pin. When the PA_IES bit (b5, INTES,...)
is ‘0’, a transition from ‘0’ to ‘1’ on the PA_S bit (b5, STAT1,...) set this bit to ‘1’; when the PA_IES bit (b5, INTES,...) is ‘1’, any
transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the PA_S bit (b5, STAT1,...) set this bit to ‘1’.
4-2
-
Reserved.
1
IBA_IS This bit indicates the interrupt status of the activate IB code.
0: No activate IB code interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Activate IB code interrupt is generated and is reported by the INT pin. When the IB_IES bit (b0, INTES,...) is ‘0’, a transition
from ‘0’ to ‘1’ on the IBA_S bit (b1, STAT1,...) set this bit to ‘1’; when the IB_IES bit (b0, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the IBA_S bit (b1, STAT1,...) set this bit to ‘1’.
0
IBD_IS This bit indicates the interrupt status of the deactivate IB code.
0: No deactivate IB code interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Deactivate IB code interrupt is generated and is reported by the INT pin. When the IB_IES bit (b0, INTES,...) is ‘0’, a transition
from ‘0’ to ‘1’ on the IBD_S bit (b0, STAT1,...) set this bit to ‘1’; when the IB_IES bit (b0, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the IBD_S bit (b0, STAT1,...) set this bit to ‘1’.
Programming Information
106
January 11, 2007