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ICSSSTUAF32865A Datasheet, PDF (10/17 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 | |||
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IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V ± 0.1V
Symbol Parameter
Min.
Max. Units
fCLOCK Clock Frequency
410
MHz
tW
tACT
tINACT
Pulse Duration; CLK, CLK HIGH or LOW
Differential Inputs Active Time1
Differential Inputs Inactive Time2
1
ns
10
ns
15
ns
DCS0 before CLKâ, CLKâ, DCS and CSGateEN
HIGH; DCS1 before CLKâ, CLKâ, DCS0 and
0.6
tSU
Setup CSGateEN HIGH3
Time DCSn, DODT, DCKE, and Dn after CLKâ, CLKâ
0.5
ns
PARIN after CLKâ, CLKâ
0.5
tH
Hold DCSn, DODT, DCKE, and Dn after CLKâ, CLKâ
0.4
Time PARIN after CLKâ, CLKâ
0.4
ns
1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of tACT(max) after RESET is taken HIGH.
2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of tINACT(max) after RESET is taken LOW.
3 tSU = 700ps for DCSx exiting Suspention Mode.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
VDD = 1.8V ± 0.1V
Symbol Parameter
Min.
Max.
fMAX Max Input Clock Frequency
410
tPDM1 Propagation Delay, single bit switching, CLKâ to CLKâ to Qn
1.1
1.5
tPDQ2 Propagation Delay, single-bit switching, CLKâ / CLKâ to Qn
0.4
0.8
tPDMSS1 Propagation Delay, simultaneous switching, CLKâ to CLKâ to Qn
1.6
tLH LOW to HIGH Propagation Delay, CLKâ to CLKâ to PTYERR
1.2
3
tHL HIGH to LOW Propagation Delay, CLKâ to CLKâ to PTYERR
1
3
tPHL HIGH to LOW Propagation Delay, RESETâ to Qnâ
3
tPLH LOW to HIGH Propagation Delay, RESETâ to PTYERRâ
3
1 Design target as per JEDEC specifications.
2 Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
Units
MHz
ns
ns
ns
ns
ns
ns
ns
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
10
IDT74SSTUBF32865A 7092/10
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