TSI384 Datasheet, PDF (1/2 Pages) Integrated Device Technology – Compliant with the following specifications

Tsi384^™ PCIe^® to PCI/X Bridge
Product Brief
®
Device Overview
The IDT Tsi384 is a high-performance bus bridge that connects the
PCI Express (PCIe) protocol to the PCI and PCI-X bus standards.
The Tsi384’s PCIe Interface has superior performance and supports
1, 2, or 4 lanes. This enables the bridge to offer exceptional throughput
performance of up to 1 GBps.
The device’s PCI/X Interface can operate up to 133 MHz in PCI-X
mode, or up to 66 MHz in PCI mode. This interface offers designers
extensive flexibility by supporting three types of addressing modes:
transparent, opaque, and non-transparent.
Low Power Consumption
The Tsi384 has typical power consumption of 1.3W, and incorporates
advanced power management to minimize power consumption during
operation. In addition to supporting D0, D3 hot, and D3 cold power
management modes, the device permits unused PCIe lanes to be
powered off automatically or by configuration.
Transparent, Non-transparent, and Opaque
Bridging
Transparent mode operation is available for efficient, flow-through
configurations, while non-transparent bridging allows isolation between
the Tsi384’s PCIe and the PCI/X domains. Non-transparent bridging also
enables multi-host systems and is used in applications such as storage
adapters. Opaque mode provides semi-transparent operation for multi-
processor configurations and enhanced private device support.
High Performance
The Tsi384 incorporates many advanced PCIe protocols that
increase system performance, including: Lane Reversal and Polarity
Inversion, end-to-end CRC, ASPM L0 link state power management,
and Hot Plug. In addition to low-latency operation, the device supports a
maximum payload size of up to 512 bytes to allow better throughput effi-
ciency.
Clocking/
Reset
PCIe Interface (x4)
EEPROM
Controller
Interrupt
Handling
Error
Handling
Posted
Writer
Buffer
Posted
Queue
Non-
Posted
Buffer
Non-
Posted
Queue
Mux Logic
Downstream
Upstream
Mux Logic
Posted
Writer
Buffer
Posted
Queue
Non-
Posted
Buffer
Non-
Posted
Queue
Power
Mgmt
Config
Registers
PCI/X
Arbiter
PCI/X Interface
JTAG
80E1000_BK001_01 (Tsi384)
Figure 1 Tsi384 Block Diagram
Features
• General
– PCI Express to PCI/PCI-X Forward bridge
– Transparent, Non-transparent, and Opaque modes
– Low latency – Superior queuing and buffering architecture
maximize throughput and minimize latency
– Compliant with the following specifications:
• PCI Express Base 1.1
• PCI Express PCI/PCI-X Bridge 1.0
• PCI-to-PCI Bridge Architecture 1.2
• PCI Local Bus 3.0
• PCI-X 2.0 (mode 1 only)
• PCI Bus Power Management Interface 1.2
 2008 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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August 13, 2009