RC32365 Datasheet, PDF (1/44 Pages) Integrated Device Technology – IDTTM InterpriseTM Integrated Communications Processor

IDT^TM Interprise^TM Integrated
Communications Processor
RC32365
Device Overview
The RC32365 device is a member of the IDT™ Interprise™ family of
integrated communications processors. This device is designed to
address a range of communications applications that require the effi-
cient processing of IPSec algorithms. These applications include gate-
ways, wireless access points, and virtual private network (VPN)
equipment. The key to the RC32365’s efficient processing of IPSec
algorithms is a highly progammable security engine which off-loads the
CPU core of encryption/decryption, hashing, and padding tasks.
Features List
◆ _{RC32300 32-bit CPU core}
– 32-bit MIPS instruction set
– Supports big or little endian operation
– MMU
– 16-entry TLB
– Supports variable page sizes and enhanced write algo-
rithm
– Supports variable number of locked entries
– 8KB Instruction Cache
– 2-way set associative
– LRU replacement algorithm
– 4 word line size
– Sub-block ordering
– Word parity
– Per line cache locking
– 2KB Data Cache
– 2-way set associative
– LRU replacement algorithm
– 4 word line size
– Sub-block ordering
– Byte parity
– Per line cache locking
– Can be programmed on a page basis to implement write-
through no write allocate, write-through write allocate, or
write-back algorithms
– Enhanced EJTAG and JTAG Interfaces
– Compatible with IEEE Std. 1149.1-1990
◆ _{Security Engine}
– Dedicated DMA channels for high speed data transfers to and
from the security engine
– On-chip memory for storage of two security contexts
– Supports ECB and CBC modes for the following symmetric
encryption algorithms: DES, triple DES (both two key (k1=k3)
and three key (k1!=k3) modes), AES-128 with 128-bit blocks,
AES-192 with 128-bit blocks
– Hardware support for encryption pad generation and checking
using one of seven popular padding algorithms: supports pad
algorithm required by IPSec ESP
– Supports MD5 and SHA-1 one-way hash functions
– Programmable truncation length of computed hash and HMAC
on a security context basis
– Supports concurrent hash and encryption operations
Block Diagram
JTAG
32-bit MIPS
CPU Core
EJTAG
MMU
D. Cache I. Cache
MII MII
Interrupt
.
Controller _.
2 Ethernet
Bus/System 10/100
Integrity ^Interfaces
Monitor
Security Functions
Security
RNG
Context Storage
Hash
Unit
Encryption
Unit
DMA
Controller
IPBus^TM
Arbiter
SDRAM & Device
Controllers
including PCMCIA
Support
3 Counter
Timers
UART
(16550)
GPIO
Interface
SPI
PCI
Controller
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus
(including PCMCIA)
Serial Channel
GPIO Pins SPI Bus
PCI Bus
Figure 1 RC32365 Internal Block Diagram
© 2005 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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October 5, 2005
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