QS5919T Datasheet, PDF (1/9 Pages) Integrated Device Technology – LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
LOW SKEW TTL PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
QS5919T
FEATURES:
• 5V operation
• Low noise TTL level outputs
• < 350ps output skew, Q0–Q4
• 2xQ output, Q outputs, Q output, Q/2 output
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Functional equivalent to Motorola MC88915
• Positive or negative edge synchronization (PE)
• Balanced drive outputs ±24mA
• 160MHz maximum frequency (2xQ output)
• Available in QSOP and PLCC packages
DESCRIPTION
The QS5919T Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight outputs
are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure <
350ps skew between the Q0-Q4, and Q/2 outputs. The QS5919T includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5919T is designed for use in high-
performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distribu-
tion networks.
For more information on PLL clock driver products, see Application Note
AN-227.
FUNCTIONAL BLOCK DIAGRAM
O E /R S T
SYNC0
SYNC1
REF_SEL
0
LOCK PE ^FEEDBACK
1
PHASE
LOOP
DETECTOR
F IL T E R
VCO
PLL_EN
FREQ_SEL
0
1
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /2
Q5
Q4
Q3
Q2
INDUSTRIAL TEMPERATURE RANGE
1
c 2000 Integrated Device Technology, Inc.
Q1
Q0
2xQ
SEPTEMBER 2000
DSC-5815/-