MPC9993 Datasheet, PDF (1/11 Pages) Motorola, Inc – INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS)
PLL Clock Driver
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
MPC9993
DATASHEET
The MPC9993 is a PLL clock driver designed specifically for redundant clock
tree designs. The device receives two differential LVPECL clock signals from
which it generates 5 new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signals frequency and phase while the other three
pairs generate 2x, phase aligned clock outputs.
Features
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3 V Operation
• 32-Lead LQFP Packaging
• 32-Lead Pb-Free Package Available
Functional Description
The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously
monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or
LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the IDCS will switch to the good secondary clock and
phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated. (See Application
Information section).
MPC9993
INTELLIGENT DYNAMIC
CLOCK SWITCH
PLL CLOCK DRIVER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
PLL_En
Clk_Selected
Inp1bad
Inp0bad
Man_Override
Alarm_Reset
Dynamic
Switch
Logic
Qb0
Sel_Clk
OR
Qb0
Qb1
CLK0
Qb1
CLK0
CLK1
8
Qb2
Qb2
CLK1
PLL
16
Qa0
Ext_FB
Qa0
Ext_FB
800 – 1600 MHz
Qa1
Qa1
MR
Figure 1. Block Diagram
MPC9993 REVISION 3 JANUARY 23, 2013
1
©2013 Integrated Device Technology, Inc.