MPC92469 Datasheet, PDF (1/12 Pages) Integrated Device Technology – 400 MHz Low Voltage PECL Clock Synthesizer w/Spread Spectrum

400 MHz Low Voltage PECL
Clock Synthesizer w/Spread
Spectrum
MPC92469
The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance tele-
com, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
400 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
w/SPREAD SPECTRUM
Features
• 25 MHz to 400 MHz synthesized clock output signal
• Differential PECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Spread Spectrum output for EMI reduction
• 3.3 V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32-lead LQFP packaging
• 32-lead Pb-free package available
• SiGe Technology
• Ambient temperature range 0°C to +70°C
• Pin compatible to the MC12429, MPC9229, MPC92429, and ICS84329
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 400
to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator
frequency f_XTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2⋅M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to V_CC – 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a eighteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAM-
MING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
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MPC92469REV 4 JANUARY 23, 2007