MK2069-03 Datasheet, PDF (1/21 Pages) Integrated Circuit Systems – VCXO-Based Clock Translator with High Multiplication

DATASHEET
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION MK2069-03
Description
The MK2069-03 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation and frequency
translation. It can accept an input clock over a wide range of
frequencies and produces a de-jittered, low phase noise
clock output. The device is optimized for user configuration
by providing access to all major PLL divider functions. No
power-up programming is needed as configuration is pin
selected. External VCXO loop filter components provide an
additional level of performance tailoring.
The MK2069-03 features a very wide range VCXO PLL
feedback divider, allowing high frequency multiplication
ratios and therefore the input of very low input reference
frequencies. The lock detector (LD) output serves as a
clock status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Features
• Wide range VCXO PLL feedback divider allows high
frequency multiplication ratios and the input of very low
input reference frequencies
• Input clock frequency of <1kHz to 13.5MHz
• Output clock frequency of 500kHz to 160MHz
• PLL lock status output
• VCXO-based clock generation offers very low jitter and
phase noise generation, even with low frequency or jittery
input clock.
• PLL Clear function (CLR input) allows the VCXO to
free-run, offering a short term holdover function.
• 2nd PLL provides frequency translation of VCXO PLL to
higher or alternate output frequencies.
• Device will free-run in the absence of an input clock (or
stopped input clock) based on the VCXO frequency
pulled to minimum frequency limit.
• Low power CMOS technology
• 56 pin TSSOP package
• Single 3.3V power supply
Block Diagram
ISET LF
P u lla b le
xtal
LFR X1
X2
SV2:0
3
IC L K
Phase
Detector
VCXO
PLL
Charge
Pump
VCXO
FV Divider
1 to 4096
SV
D iv id e r
1,2,4,6,8,
10,12,16
FPV Divider
2 to 65
CLR
12
FV11:0
6
FPV5:0
R T 1:0
2
ST1:0
2
RT
D iv id e r
1 to 4
VCO
ST
D iv id e r
2,4,8,16
T ra n s la to r
PLL
FT Divider
1 to 64
Lock Detector
LDC
LDR
6
FT5:0
VDD
4
4
GND
VCLK
OEV
TCLK
OET
RCLK
OER
LD
OEL
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 1
MK2069-03 REV J 030906