MC68150 Datasheet, PDF (1/40 Pages) Integrated Device Technology – 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer

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DATA SHEET
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NOT RECOMMENDED FOR NEW DESIGNS
The MC68150 Dynamic Bus Sizer is designed to allow the 32-bit
MC68/LC/EC040 bus, or other 16- to 32-bit processors, to communicate
bi-directionally with 32-, 16-, or 8-bit peripherals and memories. It
dynamically recognizes the size of the selected peripheral/memory and
then writes or reads the appropriate data to or from that location. Systems
designed using the bus sizing feature built into the 68030 can now be
easily upgraded to the 68/EC040 by incorporating the MC68150. The
68150 comes in two speed grades: 25/33MHz and 40MHz. These
frequencies correspond to their 68040 counterparts. The two grades
should be ordered as the MC68150FN33 and MC68150FN40,
respectively.
Typical operations which call for bus sizing are booting up instructions
from 8-bit ROM (EPROM, EEPROM, etc.) and communicating with 8-bit
SRAM’s for scratch pad memory storage during interrupt operations. The
dynamic property is necessary because the processor does not always
know the size of the peripheral it is accessing, as in the case of
communicating with a 16-bit VME bus. The MC68150 can also be used to
separate a 32-bit “Fast Bus” and an 8-, 16-, or 32-bit “Slow Bus”. (See
Figure 3)
MC68150 ^MC68150
DYNAMIC
READ/WRITE
BUS SIZER
26
61
Features
• Allows MC68/LC/EC040 or Other ‘040 Based Controllers or 68060 to
Communicate With 8-Bit Memories and Any MC68XXX Peripheral
• Also Allows Other RISC Processors to Communicate With 8-Bit and
16-Bit Peripherals
• Recognizes the Port (Peripheral) Size Dynamically
• Generates Byte/Word Address to the Dynamic Port
• Generates Byte WRITE Enable Signals For 16- and 8-bit Ports
• Sends a Transfer Acknowledge Signal to the Processor When a
Transfer Is Completed
• Synchronization of Data Transfer on Dynamic Port Allows Use of Any
Speed Peripheral
9 10
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1. Overview of Chip Operation
Each access through the MC68150 is started with a chip select (CS) assertion to the MC68150 - which is generated when a
PAL sees a TS signal from the ‘040 - and completed with a transfer acknowledge (TA) from the MC68150 to the MC68040. The
MC68150 has two distinct buses, the MPU bus and the peripheral bus. The MPU bus connects to the processor and includes the
transfer control signals (A1, A0, SIZ1, SIZ0, and R/W), the chip select (CS), the transfer acknowledge (TA) and the data bus
signals (D31-D0). The peripheral bus consists of the peripheral transfer control signals (SWE, UWE, LWE, DS, PA1, PA0), and
the peripheral transfer acknowledge signals (DSACK1, DSACK0) and the peripheral data bus (PD31-PD16).
If a 32-bit peripheral bus is used, then two additional transceivers (e.g. MC74F245) are required for the lower two bytes of the
data. These transceivers would be connected to the PD15-PD0 pins on the peripheral side and to the corresponding D15-D0 pins
on the MPU bus. The transfer direction is controlled with the R/W signal of the processor. The transceivers are enabled only when
making an access to a 32-bit port. The D15-D0 pins of the MPU bus on the MC68150 are always disabled until the port size is
known, to avoid bus contention when the port is 32-bits.
An access refers to the complete transaction through the MC68150. On the peripheral bus, an access is split into one, two, or
four separate transfers.
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MC68150 JULY 30, 2009