IDTV105ADAG Datasheet, PDF (1/19 Pages) Integrated Device Technology – DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER

DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER
DATASHEET
ADVANCE INFORMATION
CONFIDENTIAL
IDTV105A
General Description
The V105A LVDS display interface transmitter is designed
to support pixel data transmission between a video
processing engine and a digital video display. The dual
channel LVDS output supports pixel rates up to 150 MHz,
enabling compatibility with 1080p and WUXGA display
resolutions.
Total 67-bit LVCMOS/LVTTL input is provided. The V105A
converts the 67 bit parallel input data into two 5-pair LVDS
(Low Voltage Differential Signaling) serial data outputs, in
odd/even pixel format. Input data can be clocked on the
rising or falling edge of the input clock (selectable). In video
applications the 35 data bits are normally divided into 10
bits for each R, G and B channel and 5 control bits (which
includes VSYNC, HSYNC and DE).
Features
• Dual 32+3-bit LVTTL input supports up to 150 MHz pixel
rate.
• Dual pixel, LVDS output supports 150 MHz pixel rate
(compatible with 1080p and WUXGA resolution)
• Internal PLL requires no external loop filter
• Selectable rising or falling clock edge for data alignment
• Compatible with Spread Spectrum clock source
• Reduced LVDS output voltage swing mode (selectable)
to minimize EMI
• Single 3.3 V supply
• Low power consumption CMOS design
• Power down mode
• Available in 144 pin LQFP package (14x14mm body size)
Block Diagram
TA1[9:0] ¹⁰
TB1[9:0] ¹⁰
TC1[9:0] ¹⁰
RES1[2:1] ²
TA2[9:0] ¹⁰
TB2[9:0] ¹⁰
TC2[9:0] ¹⁰
RES2[2:1] ²
HSYNC
VSYNC
DE
CTRL ³
MAP
R/F
RS
PD
TEST
35
TTL Input
Data latch,
Bit Mapper,
Demux
Data
Serializer
35
Data
Serializer
CLKIN
PLL and
Device Timing
TXA1+
TXA1-
TXB1+
TXB1-
TXC1+
TXC1-
TXD1+
TXD1-
TXE1+
TXE1-
TXD2+
TXD2-
TXE2+
TXE2-
TXA2+
TXA2-
TXB2+
TXB2-
TXC2+
TXC2-
TCLK1+
TCLK1-
TCLK2+
TCLK2-
DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER
1
CONFIDENTIAL
IDTV105A
7121/3