IDTRC5000 Datasheet, PDF (1/16 Pages) Integrated Device Technology – MULTI-ISSUE 64-BIT MICROPROCESSOR

MULTI-ISSUE
64-BIT MICROPROCESSOR
IDT RC5000
Integrate d Device Tech nology, Inc.
FEATURES
• Dual issue super-scalar execution core, executing at
high-frequency
- 250 MHz frequency
- Dual issue floating-point ALU operations with other
instruction classes
- Traditional 5-stage pipeline, minimizes load and
branch latencies
- Single cycle repeat rate for most floating point ALU
operations
• High level of performance for a variety of applications
- High-performance 64-bit integer unit achieves 330
dhrystone MIPS (dhrystone 2.1)
- Ultra high-performance floating-point accelerator,
directly implementing single- and double-precision
operations achieves 500mflops
- Extremely large on-chip primary caches
- On-chip secondary cache controller
• Large, efficient on-chip caches
- 32KB Instruction Cache, 32KB Data Cache
- 2-set associative in each cache
- Virtually indexed and physically tagged to minimize
cache flushes
- Write-back and write-through selectable on a per
page basis
- Critical word first cache miss processing
- Supports back-to-back loads and stores in any com-
bination at full pipeline rate
• High-performance memory system
- Large primary caches integrated on-chip
- Secondary cache control interface on-chip
- High-frequency 64-bit bus interface runs up to
100MHz
- Aggregate bandwidth of on-chip caches, system
interface of 5GB/s
- High-performance write protocols for graphics and
data communications
• MIPS-IV 64-bit ISA for improved computation
- Compound floating-point operations for 3D graphics
and floating-point DSP
- Conditional move operations
• Compatible with a variety of operating systems
- Windows™ CE
- Numerous MIPS-compatible real-time operating sys-
tems
• Uses input system clock, with processor pipeline
clock multiplied by a factor of 2-8
• Large on-chip TLB
• Active power management, including use of WAIT
operation
BLOCK DIAGRAM
Data Set A
Store Buffer
Control
Write Buffer
Read Buffer
Data Set B
DBus
Floating Point Register File
Unpacker/Packer
Floating Point
MAdd,Add,Sub, Cvt
Div, SqRt
SysAD
Phase Lock Loop
Data Tag A
DTLB Physical
FPIBus
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Tag
AuxTag
Joint TLB
Coprocessor 0
System/Memory
Control
PC Incrementer
DVA
IVA
Branch Adder
Instruction TLB Virtual
Program Counter
Instruction Set A
Instruction Select
Integer Instruction Register
FP Instruction Register
Instruction Set B
IntIBus
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
ABus
Integer Multiply, Divide
The IDT logo is a registered trademark and ORION, R4600, R4640, R4650, R4700, R5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc. MIPS is a registered
trademark of MIPS Computer Systems, Inc.
COMMERCIAL TEMPERATURE RANGE
© 1998 Integrated Device Technology, Inc.
June, 1998
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