IDTF1912NCGI_17 Datasheet, PDF (1/22 Pages) Integrated Device Technology – 6 Bit Digital Step Attenuator

6 Bit Digital Step Attenuator
GENERAL DESCRIPTION
This document describes the specification for the IDT
F1912 Digital Step Attenuator. The F1912 is part of a
family of Glitch-Free^TM DSAs optimized for the
demanding requirements of Base Station (BTS) radio
cards and numerous other non-BTS applications.
These devices are offered in a compact 4mm x 4mm
20 pin QFN package with 50Ω impedances for ease of
integration.
COMPETITIVE ADVANTAGE
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The F1912 is a
6-bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (> +60 dBm IIP3.) The device
has pinpoint accuracy. Most importantly, the F1912
includes IDT’s Glitch-Free^TM technology which results in
low overshoot & ringing during MSB transitions.
 Glitch-Free^TM Technology so PA or ADC will not
be damaged during when transitions.
 Extremely accurate with low distortion.
 Lowest insertion loss for best SNR
APPLICATIONS
 Base Station 2G, 3G, 4G, TDD radio cards
 Repeaters and E911 systems
 Digital Pre-Distortion
 Point to Point Infrastructure
 Public Safety Infrastructure
 WIMAX Receivers and Transmitters
 Military Systems, JTRS radios
 RFID handheld and portable readers
 Cable Infrastructure
ORDERING INFORMATION
Omit IDT
prefix
0.8 mm height
package
Tape &
Reel
IDTF1912NCGI8
RF product Line
Green
IDTF1912NCGI
Datasheet
1 MHz to 4000 MHz
FEATURES
 Serial & 6 bit Parallel Interface
 31.5 dB Control Range
 0.5 dB step
 Glitch-Free^TM, low transient overshoot
 3.0 V to 5.25 V supply
 1.8 V or 3.3 V control logic
 Attenuation Error < 0.22 dB @ 2 GHz
 Low Insertion Loss < 1.6 dB @ 2 GHz
 Ultra linear IIP3 >+59.5 dBm
 IIP2 = +110 dBm typical
 Stable Integral Non-Linearity over temperature
 Low Current Consumption 550 µA typical
 -40 °C to +105 °C operating temperature
 4mm x 4mm Thin QFN 20 pin package
FUNCTIONAL BLOCK DIAGRAM
RF₁
Glitch-Free^TTMM
RF₂
Bias
Decoder
SPI
VMODE
D[5:0]
CLK DATA LE
Part# Details
Part#
F1950
Freq Range
(MHz)
150 - 4000
Resolution /
Range (dB)
0.25 / 31.75
Control
Parallel &
Serial
IL
(dB)
1.3
Pinout
PE43702
PE43701
F1951 100 - 4000 0.50 / 31.5 Serial Only 1.2 HMC305
F1952 100 – 4000 0.50 / 15.5 Serial Only 0.9 HMC305
F1953 400 – 4000
0.50 / 31.5
Parallel &
Serial
1.3
PE4302
DAT-31R5
F1956 1 - 4000
0.25 / 31.75
Parallel &
Serial
1.4
PE43705,
RFSA3715
F1912 1 – 4000
0.50 / 31.5
Parallel &
Serial
1.4
PE4312
PE4302
Glitch-Free^TM, Digital Step Attenuator
1
Rev 1, May 2017