IDTCV193 Datasheet, PDF (1/21 Pages) Integrated Device Technology – PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS

IDTCV193
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
LP/S CLOCK FOR INTEL BASED
SYSTEMS
IDTCV193
ADVANCE
INFORMATION
FEATURES:
• Compliant with Intel CK505 Gen II spec
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC, SSC and N programming
• One high precision PLL for SATA/PCI, and SSC
• One high precision PLL for 96MHz/48MHz
• Push-pull IOs for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, byte read/write
• Available in TSSOP package
KEY FEATURES
• Direct CPU and SRC clock frequency programming—write the
Hex number into Byte [16:18], 1MHz stepping.
• Linear and smooth transition for the CPU and SRC frequency
programming.
• SATA PLL source hardware select latch pin, PLL2 or PLL4.
• Internal serial resistor hardware enable latch pin.
• WOL 25MHz support.
OUTPUTS:
• 2 - 0.7V differential CPU CLK pair
• 10 - 0.7V differential SRC CLK pair
• 1 - CPU_ITP/SRC differential clock pair
• 1 - SRC0/DOT96 differential clock pair
• 6 - PCI, 33.3MHz
• 1 - 48MHz
• 1 - REF
• 1 - SATA
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
• All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II
phase noise requirement.
• SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal
interpair skew = 0 ps
FUNCTIONAL BLOCK DIAGRAM
XTAL_IN
XTAL_OUT
SDATA
SCLK
XTAL
Osc Amp
SM Bus
Controller
CKPWRGD/PD#
CPU_STOP#
PCI_STOP#
SRC5_EN
ITP_EN
CR_[H:A]#
FSC,B,A
SATA_SEL
SR_ENABLE
Control
Logic
PLL1
SSC
N Programmable
PLL3
SSC
PLL4
SSC
N Programmable
Fixed PLL
PLL2
CPU
Output Buffer
Stop Logic
PCI/SATA
SRC CLK
Output Buffer
Stop Logic
SRC CLK
Output Buffer
Stop Logic
48MHz/96MHz
Output BUffer
REF
CPU[1:0]
CPU_ITP/SRC8
SRC1/25MHz/24.576MHz
PCI[4:0], PCIF5
SATA/SRC2
SRC[7:3], [11:9]
48MHz
DOT96/SRC0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 2005 Integrated Device Technology, Inc.
IDT CONFIDENTIAL
1
APRIL 8, 2009
DSC 7165