IDTCV174CPVG Datasheet, PDF (1/21 Pages) Integrated Device Technology – PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

IDTCV174C
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV174C
FEATURES:
• Compliant with Intel CK505
• Power management control suitable for low power applications
• One high precision PLL for CPU/SRC/PCI, SSC and N program-
ming
• One high precision PLL for SRC/PCI, SSC and N programming
• One high precision PLL for 96MHz/48MHz
• Push-pull IOs for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength
• Smooth transition for N programming
• Available in SSOP and TSSOP packages
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
DESCRIPTION:
IDTCV174C is a 56 pin clock device, incorporating Intel CK505 requirements
for the Intel advance P4 processor. The CPU output buffer is designed to
support up to 400MHz reference clock for the CPU. This chip has three PLLs
inside for CPU, SRC/PCI and 48MHz/DOT96 IO clocks.
OUTPUTS:
• 2*0.7V differential CPU CLK pair
• 7*0.7V differential SRC CLK pair
• One CPU_ITP/SRC differential clock pair
• One SRC0/DOT96 differential clock pair
• 6*PCI, 33.3MHz
• 1*48MHz
• 1*REF
• 1*SATA
FUNCTIONAL BLOCK DIAGRAM
XTAL_IN
XTAL_OUT
SDATA
SCLK
XTAL
Osc Amp
SM Bus
Controller
CKPRWGD/PD#
CPU_STOP#
PCI_STOP#
SRC5_EN, LTE
ITP_EN
CR#_[F:A]
FSC,B,A
Control
Logic
PLL1
SSC
N Programmable
PLL3
SSC
N Programmable
Fixed PLL
PLL2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
CPU, SRC, PCI
Output Buffer
Stop Logic
SRC CLK
Output Buffer
Stop Logic
48MHz/96MHz
Output BUffer
REF
CPU[1:0]
CPU_ITP/SRC8
SRC[7:1]
PCI[4:0], PCIF5
SATA
48MHz
DOT96/SRC0
MAY 2006
DSC 6898/8