IDTCV144 Datasheet, PDF (1/25 Pages) Integrated Device Technology – PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

IDTCV144
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV144
FEATURES:
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
• One high precision PLL for LVDS. Supports 100/96MHz output
frequency, SSC programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less execution-
intensive
• Smooth transition for N programming
• Available in TSSOP package
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error for all clocks = 0ppm
DESCRIPTION:
IDTCV144 is a 56 pin clock device, incorporating both Intel CK410M and
CKSSCD requirements, for Intel advance P4 processors. The CPU output
buffer is designed to support up to 400MHz processor. This chip has four PLLs
inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device
also implements Band-gap referenced IREF to reduce the impact of VDD variation
on differential outputs, which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, worse case 114
ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own
Spread Spectrum selection.
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 5*0.7V current –mode differential SRC CLK pair
• One CPU_ITP/SRC selectable CLK pair
• 6*PCI, 2 free running, 33.3MHz
• 1*96MHz, 1*48MHz
• 2*REF
• One 100/96 MHz differential LVDS
FUNCTIONAL BLOCK DIAGRAM
X1
X2
SDATA
SCLK
XTAL
Osc Amp
SM Bus
Controller
PLL1
SSC
N Programmable
PLL2
SSC
VTT_PWRGD#/PD
SEL100/96#
CLKREQA#
CLKREQB#
FSA.B.C
PCI_STOP#
CPU_STOP#
SEL
100/96MHz
Control
Logic
PLL3
SSC
N Programmable
PLL4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
CPU CLK
Output Buffer
Stop Logic
IREF
LVDS CLK
Output Buffer
Stop Logic
IREF
SRC CLK
Output Buffer
Stop Logic
IREF
48MHz/96MHz
Output BUffer
ITP_EN
CPU[1:0]
CPU_ITP/SRC7
REF
LVDS
SRC[5:1]
PCI[3:0], PCIF[1:0]
48MHz
DOT96
DECEMBER 2004
DSC 6597/3