IDTCSPT857A Datasheet, PDF (1/12 Pages) Integrated Device Technology – 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
IDTCSPT857/A
FEATURES:
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
DESCRIPTION:
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential output
pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the output frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857 is only available in Industrial Temperature Range (-40°C to
+85°C), and CSPT857A is only available in Commercial Temperature Range
(0°C to +70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
37/E6
PWRDWN
AVDD ^16/G2
TEST
MODE
LOGIC
CLK
CLK
13/F1
14/F2
FBIN
FBIN
36/F6
35/F5
PLL
3/A1
Y0
2/A2
Y0
5/B2
Y1
6/B1 _Y1
10/D1
Y2
9/D2
Y2
20/J2
Y3
19/J1
Y3
22/K1
Y4
23/K2
Y4
46/A6
Y5
47/A5
Y5
44/B5
Y6
43/B6 _Y6
39/D6
Y7
40/D5 _Y7
29/J5 _Y8
30/J6 _Y8
27/K6 _Y9
26/K5
Y9
32/H6
33/H5
FBOUT
FBOUT
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2002 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
OCTOBER 2002
DSC-5172/8