IDT8V89317 Datasheet, PDF (1/9 Pages) Integrated Device Technology – Input references are monitored for frequency offset and activity

10G Ethernet PLL and IEEE 1588
Synthesizer for Industrial Automa-
Short Form Datasheet
IDT8V89317
FEATURES
HIGHLIGHTS
• Digital PLL locks to GPS or Ethernet physical layer clocks
• Provides clocks for 1 Gigabit and 10 Gigabit Ethernet, QSGMII and
XAUI
• Internal Digitally Controlled Oscillator supports IEEE 1588 clocks
generation
• Jitter generation <0.3ps RMS (10 kHz to 20 MHz), meets jitter
requirements of leading PHYs supporting 10GBASE-R, QSGMII
and XAUI
MAIN FEATURES
• Digital PLL synchronizes with GPS or Ethernet connected synchro-
nization sources
• DPLL bandwidth is selectable to be 15 mHz or 1.2 Hz
• DPLL holdover accuracy is 1.1X10-5 ppm and instantaneous hold-
over accuracy is 4.4X10-8 ppm
• Input references are monitored for frequency offset and activity
• DPLL holdover, free run and hitless reference switching can be
forced by the host processor or can be automatically controlled by
an internal state machine
• Internal DCO has resolution of 0.01105 ppb and can be controlled
by an external processor via I2C interface for IEEE 1588 clock gen-
eration
• Two Analog PLLs for jitter attenuation and frequency translation
• IN1, IN2 and IN3 accept single ended reference clocks whose fre-
quencies can be 1PPS (1 Hz), 25 MHz, 125 MHz or 156.25 MHz
• OUT1 and OUT2 output differential clocks with frequencies of 125
MHz or 156.25 MHz
• OUT3 outputs a differential clock with frequency of
322.265625 MHz or 644.53125 MHz
• OUT4 outputs a free-running LVCMOS clock with frequency of 
25 MHz
OTHER FEATURES
• I2C microprocessor interface mode
• IEEE 1149.1 JTAG Boundary Scan
• 1mm ball pitch CABGA green package
APPLICATIONS
• Industrial Automation
• Power Systems
Crystal
IN1
Input Pre-Divider Priority
IN2
Input Pre-Divider Priority
IN3
Input Pre-Divider Priority
Monitors
Input
Selector
DPLL/
DCO
APLL1
(VCXO)
I2C
IN_APLL1_POS
IN_APLL1_NEG
IN_APLL2_POS
IN_APLL2_NEG
Microprocessor Interface
JTAG
APLL
APLL2
(VCXO)
OSCI
Crystal
Figure 1. Functional Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
IEEE 1588^TM is a trademark of its respective owner
1
 2014 Integrated Device Technology, Inc.
DSC-7238/-
Divider
Divider
Divider
OUT1_POS
OUT1_NEG
OUT2_POS
OUT2_NEG
OUT3_POS
OUT3_NEG
OUT4
May 5, 2014
IDT CONFIDENTIAL