IDT8V89316 Datasheet, PDF (1/9 Pages) Integrated Device Technology – Input references are monitored for frequency offset and activity

Ethernet PLL and IEEE 1588 Synthesizer
for Industrial Automation and Power
Short Form Datasheet
IDT8V89316
FEATURES
HIGHLIGHTS
• Digital PLL locks to Ethernet physical layer clocks
• Provides clocks for 1 Gigabit Ethernet and QSGMII
• Internal Digitally Controlled Oscillator supports IEEE 1588 clock
generation
• Jitter generation <0.65 ps RMS (10 kHz to 20 MHz) meets jitter
requirements of 1 GbE PHYs and QSGMII
MAIN FEATURES
• Digital PLL synchronizes with Ethernet connected synchronization
sources
• DPLL bandwidth of 1.2 Hz
• DPLL holdover accuracy is 1.1X10-5 ppm and instantaneous hold-
over accuracy is 4.4X10-8 ppm
• Input references are monitored for frequency offset and activity
• DPLL holdover, free run and hitless reference switching can be
forced by the host processor or can be automatically controlled by
an internal state machine
• Internal DCO has resolution of 0.01105 ppb and can be controlled
by an external processor via I2C interface for IEEE 1588 clock gen-
eration
• One Analog PLL for jitter attenuation
• IN1, IN2 and IN3 accept single ended reference clocks whose fre-
quencies can be 25 MHz, 125 MHz or 156.25 MHz
• OUT1 outputs a differential clock with frequency of 125 MHz or
156.25 MHz
• OUT2 to OUT6 output differential clocks all with the same fre-
quency of 125 MHz or 156.25 MHz
• OUT7 outputs a free-running LVCMOS clock with frequency of 25
MHz
OTHER FEATURES
• I2C microprocessor interface mode
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 1mm ball pitch CABGA green package
APPLICATIONS
• Industrial Automation
• Power Systems
Crystal
IN1
Input Pre-Divider Priority
IN2
Input Pre-Divider Priority
IN3
Input Pre-Divider Priority
Monitors
Input
Selector
DPLL/
DCO
APLL
I2C
IN_APLL_POS
IN_APLL_NEG
Microprocessor Interface
JTAG
APLL
Divider
Divider
OUT1_POS
OUT1_NEG
OUT2_POS
OUT2_NEG
OUT3_POS
OUT3_NEG
OUT4_POS
OUT4_NEG
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
OUT7
OSCI
Figure 1. Functional Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
IEEE 1588^TM is a trademark of its respective owner
1
 2014 Integrated Device Technology, Inc.
DSC-7238/-
May 5, 2014
IDT CONFIDENTIAL