IDT8T49N205I Datasheet, PDF (1/41 Pages) Integrated Device Technology – Fourth Generation FemtoClock

FemtoClock^® NG Universal Frequency
Translator with Phase Build-Out
IDT8T49N205I
DATA SHEET
General Description
The IDT8T49N205I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
Phase Build-Out (PBO) suitable for networking and communications
applications. It is able to generate any output frequency in the
0.98MHz - 312.5MHz range and most output frequencies in the
312.5MHz - 1,300MHz range (see Table 3 for details). A wide range
of input reference clocks and a range of low-cost fundamental mode
crystal frequencies may be used as the source for the output
frequency.
The IDT8T49N205I has three operating modes to support a very
broad spectrum of applications:
1 Frequency Synthesizer
• Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
• Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
2) High-Bandwidth Frequency Translator
• Applications: PCI Express, Computing, General Purpose
• Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
• This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
3) Low-Bandwidth Frequency Translator
• Applications: Networking & Communications.
• Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-12 option requiring a 622.08MHz
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet
option requiring a 125MHz LVPECL clock translated from the same
19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I²C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written next time the device powers-up.
Features
• Fourth Generation FemtoClock® NG technology
• Universal Frequency Translator/Frequency Synthesizer
• Zero ppm frequency translation
• Two outputs, individually programmable as LVPECL or LVDS
• Both outputs may be set to use 2.5V or 3.3V output levels
• Programmable output frequency: 0.98MHz up to 1,300MHz
• Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
• Input frequency range: 8kHz - 710MHz
• Phase Build-Out minimizes output phase change on switchover
• Crystal input frequency range: 16MHz - 40MHz
• Two factory-set register configurations for power-up default state
• Power-up default configuration pin or register selectable
• Configurations customized via One-Time Programmable ROM
• Settings may be overwritten after power-up via I²C
• I²C Serial interface for register programming
• RMS phase jitter at 155.52MHz, using a 40MHz crystal
(12kHz - 20MHz): 378fs (typical), Low Bandwidth Mode (FracN)
• Output supply voltage modes:
V_CC/V_CCA/V_CCO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V
2.5V/2.5V/2.5V
• -40°C to 85°C ambient operating temperature
Pin Assignment
CLK_ACTIVE
nc
LF0
LF1
VEE
VCCA
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
30 29 28 27 26 25 24 23 22 21
31
20
32
19
33 IDT8T49N205I 18
34 _{40 Lead VFQFN}
17
35 _{6mm x 6mm x 0.925mm} 16
36 _{EPad 4.65mm x 4.65mm} 15
37
NL Package
14
38
13
39
Top View
12
40
11
1 2 3 4 5 6 7 8 9 10
nc
nc
S_A0
S_A1
CONFIG
SCLK
SDATA
VCC
PLL_BYPASS
nc
IDT8T49N205ANLGI REVISION B JULY 9, 2013
1
©2013 Integrated Device Technology, Inc.