IDT8T39S10I Datasheet, PDF (1/43 Pages) Integrated Device Technology – Two differential reference clock input pairs

Crystal or Differential to Differential
Clock Fanout Buffer
IDT8T39S10I
DATASHEET
General Description
The IDT8T39S10I is a high-performance clock fanout buffer. The
input clock can be selected from two differential inputs or one crystal
input. The internal oscillator circuit is automatically disabled if the
crystal input is not selected. The crystal pin can be driven by
single-ended clock when crystal is bypassed.The selected signal is
distributed to ten differential outputs which can be configured as
LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is
provided. All outputs can be disabled into a high-impedance state.
The device is designed for signal fanout of high-frequency, low
phase-noise clock and data signal. The outputs are at a defined level
when inputs are open circuit or tied to ground. It is designed to
operate from a 3.3V or 2.5V core power supply, and either a 3.3V or
2.5V output operating supply.
Features
• Two differential reference clock input pairs
• Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
• Two banks, each has five differential output pairs that can be
configured as LVPECL or LVDS or HCSL
• One single-ended reference output with synchronous enable to
avoid clock glitch
• Output skew: (Bank A and Bank B at the same output level)
70ps (max)
• Part-to-part skew: 250ps (max)
• Additive RMS phase jitter: 0.153ps (typical)
• Supply voltage modes:
V_DD/V_DDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
IDT8T39S10NLGI REVISION A MARCH 18. 2014
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©2014 Integrated Device Technology, Inc.