IDT8SLVP1102I Datasheet, PDF (1/22 Pages) Integrated Device Technology – Maximum input clock frequency

Low Phase Noise, 1-to-2, 3.3V, 2.5V
LVPECL Output Fanout Buffer
IDT8SLVP1102I
DATASHEET
General Description
The IDT8SLVP1102I is a high-performance differential LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
IDT8SLVP1102I is characterized to operate from a 3.3V or 2.5V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVP1102I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and two low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device input. The device is
optimized for low power consumption and low additive phase noise.
Features
• Two low skew, low additive jitter LVPECL output pairs
• Differential PCLK, nPCLK pair can accept the following differential
input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• Output skew: 5ps (typical)
• Propagation delay: 250ps (maximum)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
12kHz - 20MHz: 49fs (maximum)
• Full 3.3V or 2.5V supply voltage
• Maximum device current consumption (I_EE): 34mA (maximum)
• Available in lead-free (RoHS 6), 16-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Block Diagram
V_CC
PCLK
nPCLK
V_REF
Voltage
Reference
Pin Assignment
Q0
nQ0
Q1
nQ1
16 15 14 13
VEE 1
12 nQ1
nc 2
11 Q1
nc 3
10 nQ0
nc 4
9 Q0
5 6 78
IDT8SLVP1102I
16-Lead VFQFN
3.0mm x 3.0mm x 0.925mm package body
NL Package
Top View
IDT8SLVP1102ANLI REVISION A FEBRUARY 25, 2014
1
©2014 Integrated Device Technology, Inc.