IDT8SLVD1208-33I Datasheet, PDF (1/21 Pages) Integrated Device Technology – Eight low skew, low additive jitter LVDS output pairs

1:8, LVDS Output Fanout Buffer
IDT8SLVD1208-33I
DATA SHEET
General Description
The IDT8SLVD1208-33I is a high-performance differential LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
IDT8SLVD1208-33I is characterized to operate from a 3.3V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVD1208-33I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Eight low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control select input
• Output skew: 8ps (typical)
• Propagation delay: 240ps (typical)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
10kHz - 20MHz: 82fs (typical)
• Maximum device current consumption (I_DD):
190mA (maximum) @ 3.465V
• 3.3V supply voltage
• Lead-free (RoHS 6), 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Pin Assignment
Q4 22
nQ4 23
Q5 24
nQ5 25
Q6 26
nQ6 27
V_DD 28
14 GND
13 nQ0
12 Q0
11 V_REF0
10 nPCLK0
9 PCLK0
8 V_DD
IDT8SLVD1208-33NBGI REVISION A FEBRUARY 12, 2014
IDT8SLVD1208-33I
28 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
E-Pad size 3.25mm x 3.25 mm
NB Package
Top View
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©2014 Integrated Device Technology, Inc.