IDT8P34S1208I Datasheet, PDF (1/18 Pages) Integrated Device Technology – Eight low skew, low additive jitter LVDS output pairs

1:8 LVDS Output 1.8V Fanout Buffer
IDT8P34S1208I
DATA SHEET
General Description
The IDT8P34S1208I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1208I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1208I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Eight low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (typical)
• Propagation delay: 315ps (typical)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
12kHz - 20MHz: 41fs (typical)
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 28-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram.
V_REF0
CLK0
nCLK0
Voltage
Reference
V_DD
f_REF
V_DD
CLK1
nCLK1
SEL
V_REF1
Voltage
Reference
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
21 20 19 18 17 16 15
Q4 22
IDT8P34S1208I
14 GND
nQ4 23
28-lead VFQFN
13 nQ0
Q5 24 ^{5.0mm x 5.0mm x 0.75mm} 12 Q0
package body
nQ5 25
11 V_REF0
Q6 26 ^{3.25mm x 3.25mm ePad Size} 10 nCLK0
nQ6 27
NB Package
9 CLK0
V_DD 28
Top View
8 V_DD
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IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
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©2014 Integrated Device Technology, Inc.