IDT8P34S1106I Datasheet, PDF (1/18 Pages) Integrated Device Technology – One differential clock input pair

1:6 LVDS Output 1.8V Fanout Buffer
IDT8P34S1106I
DATA SHEET
General Description
The IDT8P34S1106I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1106I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1106I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and six low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the differential device input. The
device is optimized for low power consumption and low additive
phase jitter.
Features
• Six low skew, low additive jitter LVDS output pairs
• One differential clock input pair
• Differential CLK, nCLK pair can accept the following differential
input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz (maximum)
• Output skew: 20ps (typical)
• Propagation delay: 290ps (typical)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
12kHz- 20MHz: 39fs (typical)
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 20-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
V_DD
CLK
nCLK
V_REF
V_REF
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014
Pin Assignment
15 14 13 12 11
Q3 16
nQ3 17
Q4 18
nQ4 19
VDD 20
Top View
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10 nQ0
9 Q0
8 V_REF
7 nCLK
6 CLK
IDT8P34S1106I
20-lead VFQFN
4mm x 4mm x 0.925mm package body
2.1mm x 2.1mm ePad Size
NL Package
Top View
1
©2014 Integrated Device Technology, Inc.