IDT8P34S1102I Datasheet, PDF (1/18 Pages) Integrated Device Technology – Two low skew, low additive jitter LVDS output pairs

1:2 LVDS Output 1.8V Fanout Buffer
IDT8P34S1102I
DATA SHEET
General Description
The IDT8P34S1102I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1102I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1102I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and two low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the differential device input. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Two low skew, low additive jitter LVDS output pairs
• One differential clock input pair
• Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz
• Output skew: 3ps (typical)
• Propagation delay: 400ps (maximum)
• Low additive phase jitter, RMS; f_REF = 156.25MHz,
12kHz- 20MHz: 42fs (typical)
• Maximum device current consumption (I_EE): 48mA
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
V_DD
CLK
nCLK
Q0
nQ0
Q1
nQ1
V_REF
V_REF
IDT8P34S1102NLGI REVISION A FEBRUARY 26, 2014
Pin Assignment
12 11 10 9
nc 13
nc 14
nc 15
GND 16
1234
8 V_REF
7 nCLK
6 CLK
5 VDD
IDT8P34S1102I
16-lead VFQFN
3mm x 3mm x 0.925mm package body
1.7mm x 1.7mm ePad Size
NL Package
Top View
1
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