IDT82V3910 Datasheet, PDF (1/13 Pages) Integrated Device Technology – Supports programmable input-to-output phase offset adjustment

Synchronous Ethernet SETS
for 10GbE and 40GbE
IDT82V3910
Short Form Datasheet
FEATURES
HIGHLIGHTS
• Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter gen-
eration requirements of leading PHYs supporting 10GBASE-R,
10GBASE-W, 40GBASE-R, OC-192 and STM-64
• Features 0.5 mHz to 35 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous Ether-
net (SyncE)
• Provides node clocks for Cellular and WLL base-station (GSM and
3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially
for Japan TCM-ISDN network timing based ADSL equipments
• Provides clocks for 1 Gigabit, 10 Gigabit, and 40 Gigabit Ethernet
• Supports clock generation for IEEE-1588 applications
MAIN FEATURES
• Provides an integrated solution for Synchronous Equipment Timing
Source, including Stratum 3, SMC, EEC-Option 1 and EEC-
Option 2 Clocks
• Integrates T4 DPLL and T0 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
• Supports programmable DPLL bandwidth (0.5 mHz to 35 Hz) and
damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10^-5 ppm absolute holdover accuracy and
4.4X10^-8 ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients
on T0 DPLL output to be no more than 0.61 ns
• Integrates 2 jitter attenuating APLLs to generate ultra-low jitter
clocks
• Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-
PHY
• Supports up to two crystal connections, allowing each APLL to
support up to two modes of operation
• Supports input and output clocks whose frequencies range from
1PPS to 644.53125 MHz
• Includes 1PPS clock input and output
• Provides IN1 and IN2 for 64 kHz + 8 kHz or
64 kHz + 8 kHz + 0.4 kHz composite clocks
• Provides IN3, IN4, IN7~IN14 input CMOS clocks whose frequen-
cies range from 1PPS to 156.25 MHz
• Provides IN5 and IN6 input differential clocks whose frequencies
range from 1PPS to 625 MHz
• Provides OUT1 to OUT5 output CMOS clocks whose frequency
cover from 1PPS to 125 MHz
• Provides OUT6,OUT7,OUT10 and OUT11 output differential
clocks whose frequency cover from 25 MHz to 644.53125 MHz
• Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/
2.048 MHz (BITS/SSU)
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,
and a 1PPS, 2 kHz or 8 kHz frame sync output signal
• Internal DCO can be controlled by an external processor to be used
for IEEE-1588 clock generation
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. Automatic mode switch supports Free-
Run, Locked and Holdover modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Supports AMI, LVPECL/LVDS and CMOS input/output technologies
• Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• I2C Microprocessor interface
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 1mm ball pitch CABGA green package
APPLICATIONS
• SMC / SEC (SONET / SDH equipment)
• EEC (Synchronous Ethernet equipment)
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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 2013 Integrated Device Technology, Inc.
July 1, 2013
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