IDT82V3011 Datasheet, PDF (1/30 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT

T1/E1/OC3 WAN PLL WITH
SINGLE REFERENCE INPUT
IDT82V3011
FEATURES
• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
4 Enhanced and Stratum 4 timing for DS1 interfaces
• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
• Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44
MHz
• Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
• Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
• Provides a C2/C1.5 output clock signal with the frequency
controlled by the reference input Fref
• Holdover frequency accuracy of 0.025 ppm
• Phase slope of 5 ns per 125 µs
• Attenuates wander from 2.1 Hz
• Fast lock mode
• Provides Time Interval Error (TIE) correction
• MTIE of 600 ns
• JTAG boundary scan
• Holdover status indication
• Freerun status indication
• Normal status indication
• Lock status indication
• Input reference quality indication
• 3.3 V operation with 5 V tolerant I/O
• Package available: 56-pin SSOP
FUNCTIONAL BLOCK DIAGRAM
TDO TDI
OSCi
TCLR
RST V_DD V_SS V_DD V_SS V_DD V_SS V_DD V_SS
TCK
TMS
TRST
FLOCK
Fref
JTAG
OSC
TIE Control
Block
Virtual
Reference
DPLL
MON_out
Reference
Input Monitor
Invalid Input
Signal
Detection
Feedback Signal
C2/C1.5
C32o
C19o
C19POS
C19NEG
C16o
C8o
C4o
C2o
C3o
C1.5o
C6o
F0o
F8o
F16o
F19o
F32o
RSP
TSP
LOCK
State Control Circuit
Input Frequency
Selection
TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun
F_sel1 F_sel0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc.
OCTOBER 22, 2003
DSC-6237/3