IDT82V2048E Datasheet, PDF (1/76 Pages) Integrated Device Technology – OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

OCTAL CHANNEL T1/E1/J1
SHORT HAUL LINE INTERFACE UNIT
IDT82V2048E
FEATURES:
- High impedance setting for line drivers
• Eight channel T1/E1/J1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 2¹⁵-1 PRBS polynomials for E1
without external relays
- QRSS (Quasi Random Sequence Signals) generation and detection
• Programmable T1/E1/J1 switchability allowing one bill of ma-
with 2²⁰-1 QRSS polynomials for T1/J1
terial for any line condition
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
error counter
• Meets or exceeds specifications in
- Analog loopback, Digital loopback, Remote loopback and Inband
- ANSI T1.102, T1.403 and T1.408
loopback
- ITU I.431, G.703,G.736, G.775 and G.823
• Adaptive receive sensitivity up to -20 dB
- ETSI 300-166, 300-233 and TBR 12/13
• Non-intrusive monitoring per ITU G.772 specification
- AT&T Pub 62411
• Short circuit protection for line drivers
• Per channel software selectable on:
• LOS (Loss Of Signal) detection with programmable LOS levels
- Wave-shaping templates
• AIS (Alarm Indication Signal) detection
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω) _{• JTAG interface}
- Adjustment of arbitrary pulse shape
• Supports serial control interface, Motorola and Intel Non-Multi-
- JA (Jitter Attenuator) position (receive path or transmit path)
plexed interfaces
- Single rail/dual rail system interfaces
• Package:
- B8ZS/HDB3/AMI line encoding/decoding
IDT82V2048E: 208-pin PQFP and 208-pin PBGA
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
DESCRIPTION:
The IDT82V2048E can be configured as an octal T1, octal E1 or octal
J1 Line Interface Unit. The IDT82V2048E performs clock/data recovery,
AMI/B8ZS/HDB3 line decoding and detects and reports the LOS condi-
tions. An integrated Adaptive Equalizer is available to increase the receive
sensitivity and enable programming of LOS levels. In transmit path, there
is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter
Attenuator for each channel, which can be placed in either the receive path
or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2048E supports both Single Rail and Dual Rail system interfaces
and both serial and parallel control interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110
Ω and 120 Ω are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
The IDT82V2048E can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
1
 2003 Integrated Device Technology, Inc. All rights reserved.
August 2004
DSC-6532/-