IDT7MPV6253 Datasheet, PDF (1/7 Pages) Integrated Device Technology – 256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPCO

Integrated Device Technology, Inc.
256KB AND 512KB SECONDARY
CACHE MODULES FOR THE
PowerPC™
IDT7MPV6253
IDT7MPV6255/56
FEATURES
• For CHRP based PowerPC™ systems.
• Asynchronous and pipelined burst SRAM options in the
same module pinout
• Low-cost, low-profile card edge module with 178 leads
• Uses Burndy Computerbus™ connector, part number
ELF182KSC-3Z50
• Operates with external PowerPC CPU speeds up to
66MHz
• Separate 5V (±5%) and 3.3V (+10/-5%) power supplies
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Presence Detect output pins allow the system to deter-
mine the particular cache configuration.
DESCRIPTION
The IDT7MPV6253/55/56 modules belong to a family of
secondary caches intended for use with PowerPC CPU-
based systems. The IDT7MPV6253 uses IDT’s 71V256 32K
x 8 asynchronous static RAMs and the IDT7MPV6255/56 use
IDT’s 71V432 32K x 32 pipelined synchronous burst static
RAMs in plastic surface mount packages mounted on a
multilayer epoxy laminate (FR-4) board. In addition, each of
the modules uses the IDT 71216 16K x 15 Cache-Tag static
RAM and IDT FCT logic. Extremely high speeds are achieved
using IDT’s high-reliability, low cost CMOS technology.
The low profile card edge package allows 178 signal leads
to be placed on a package 5.06" long, a maximum of 0.250"
thick and a maximum of 1.08" tall. The module space savings
versus discrete components allows the OEM to design addi-
tional functions onto the system or to shrink the size of the
motherboard for reduced cost.
All inputs and outputs are LVTTL-compatible, and operate
from separate 5V (±5%) and 3.3V (+10/-5%) power supplies.
Multiple GND pins and on-board decoupling capacitors en-
sure maximum protection from noise.
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6253 – 256KB ASYNCHRONOUS VERSION
A14 - A26 ¹³
13
ALE
ADDRA0
ADDRA1
SRAM OE1
WE#0
WE#1
WE#2
WE#3
STANDBY
A14 - A26 ¹³
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK2
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
8K x 12
Tag Field
8K x 2
Status
ADDRA0
ADDRA1
SRAM OE0
8
DH0 - DH7 WE#4
8
DH8 - DH15 WE#5
8
DH16 - DH23 WE#6
8
DH24 - DH31 WE#7
STANDBY
12
A2 - A13
TMATCH
DIRTYOUT
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
1
PD0
PD1
PD2
PD3
8
DL0 - DL7
8
DL8 - DL15
8
DL16 - DL23
8
DL24 - DL31
drw 01
JUNE 1996
DSC-3608/2