IDT7MP4120 Datasheet, PDF (1/8 Pages) Integrated Device Technology – 1M x 32 CMOS STATIC RAM MODULE

1M x 32
CMOS STATIC RAM MODULE
IDT7MP4120
Integrated Device Technology, Inc.
FEATURES
• High-density 4MB Static RAM module
• Low profile 72-pin ZIP (Zig-zag In-line vertical Package)
or 72-pin SIMM (Single In-line Memory Module)
• Fast access time: 20ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Inputs/outputs directly TTL-compatible
PIN CONFIGURATION⁽¹⁾
NC 2
PD3 4
PD0 6
I/O0 8
I/O1 10
I/O2 12
I/O3 14
VCC 16
A7 18
A8 20
A9 22
I/O4 24
I/O5 26
I/O6 28
I/O7 30
WE 32
A14 34
CS1 36
1 NC
3 PD2
5 GND
7 PD1
9 I/O 8
11 I/O 9
13 I/O 10
15 I/O 11
17 A0
19 A1
21 A2
23 I/O 12
25 I/O 13
27 I/O 14
29 I/O 15
31 GND
33 A15
35 CS2
PD0 - GND
PD1 - NC
PD2 - GND
PD3 - NC
CS3 38
A16 40
GND 42
I/O 16 44
I/O 17 46
I/O 18 48
I/O 19 50
A10 52
A11 54
A12 56
A13 58
I/O 20 60
I/O 21 62
I/O 22 64
I/O 23 66
GND 68
A19 70
NC 72
37 CS4
39 A17
41 OE
43 I/O 24
45 I/O 25
47 I/O 26
49 I/O 27
51 A3
53 A4
55 A5
57 VCC
59 A6
61 I/O 28
63 I/O 29
65 I/O 30
67 I/O 31
69 A18
71 NC
ZIP, SIMM
TOP VIEW
3019 drw 01
NOTE:
1. Pins 3, 4, 6 and 7 (PD0, PD1, PD2 and PD3 respectively) are read by the
user to determine the density of the module. If PD0 reads GND, PD1 reads
NC, PD2 reads GND and PD3 reads NC, then the module has a 1M depth.
The IDT logo is a registered trademark of Integrated Device Technology Inc.
DESCRIPTION
The IDT7MP4120 is a 1M x 32 Static RAM module con-
structed on an epoxy laminate (FR-4) substrate using 8 1M x
4 Static RAMs in plastic packages. Availability of four chip
select lines (one for each group of two RAMs) provides byte
access. The IDT7MP4120 is available with access time as fast
as 20ns with minimal power consumption.
The IDT7MP4120 is packaged in a 72-pin FR-4 ZIP (Zig-
zag In-line vertical Package)or a 72-pin SIMM (Single In-line
Memory Module). The ZIP configuration allows 72 pins to be
placed on a package 4.05" long and 0.365" wide. At only 0.60"
high, this low-profile package is ideal for systems with mini-
mum board spacing while the SIMM configuration allows use
of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4120 are TTL-com-
patible and operate from a single 5V supply. Full asynchro-
nous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
Four identification pins (PD0, PD1, PD2 and PD3) are pro-
vided for applications in which different density versions of the
module are used. In this way, the target system can read the
respective levels of PD0, PD1, PD2 and PD3 to determine a 1M
depth.
The contact pins are plated with 100 micro-inches of nickel
covered by 30 micro-inches minimum of selective gold.
FUNCTIONAL BLOCK DIAGRAM
CS1 CS2 CS3 CS4
20
A0 – A19
WE
OE
1M x 32
RAM
3 _{PD0 – PD3}
8
8
8
8
I/O0-7 I/O8-15 I/O16-23 I/O24-31
3019 drw 02
PIN NAMES
I/O0–I/O31
A0–A19
CS1–CS4
WE
OE
PD0–PD3
VCC
GND
NC
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
No Connect
3019 tbl 01
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
7.07
SEPTEMBER 1996
DSC-3019/5
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