IDT79RC4640_08 Datasheet, PDF (1/23 Pages) Integrated Device Technology – Low-Cost Embedded 64-bit RISController w/ DSP Capability

Low-Cost Embedded
64-bit RISController
w/ DSP Capability
IDT79RC4640^™
Features
◆ _{High-performance embedded 64-bit microprocessor}
– 64-bit integer operations
– 64-bit registers
– Based on the MIPS RISC Architecture
– 100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz
operating frequencies
– 32-bit bus interface brings 64-bit power to 32-bit system cost
◆ _{High-performance DSP capability}
– 133.5 Million Integer Mul-Accumulate
operations/sec @267MHz
– 89 MFlops floating-point operations @267MHz
◆ _{High-performance microprocessor}
– 133.5 M Mul-Add/second @267MHz
– 89 MFlops @267MHz
– >640,000 dhrystone (2.1)/sec capability @267MHz (352
dhrystone MIPS)
◆ _{High level of integration}
– 64-bit, 267 MHz integer CPU
– 8KB instruction cache; 8KB data cache
– Integer multiply unit with 133.5M Mul-Add/sec
◆ _{Upwardly software compatible with IDT RISController}
Family
◆ _{Easily upgradable to 64-bit system}
◆ _{Low-power operation}
– Active power management powers-down inactive units
– Standby mode
◆ _{Large, efficient on-chip caches}
– Separate 8KB Instruction and 8KB Data caches
– Over 3200MB/sec bandwidth from internal caches
– 2-set associative
– Write-back and write-through support
– Cache locking, to facilitate deterministic response
– High performance write protocols, for graphics and data
communications
◆ _{Bus compatible with RC4000 family}
– System interfaces to 125MHz, provides bandwidth up to 500
MB/sec
– Direct interface to 32-bit wide systems
– Synchronized to external reference clock for multi- master
operation
– Socket compatible with IDT RC 64474 and RC64574
◆ _{Improved real-time support}
– Fast interrupt decode
– Optional cache locking
Note: “R” refers to 5V parts; “RV” refers to 3.3V parts; “RC”
refers to both
Block Diagram
267 MHz 64-bit CPU
64-bit Register File
64-bit Adder
Load Aligner
Store Aligner
Logic Unit
High-Performance
Integer Multiply
System Control Coprocessor
Address Translation/
Cache Attribute Control
Exception Management
Functions
89 MFlops Single-Precision FPA
FP Register File
Pack/Unpack
FP Add/Sub/Cvt/
Div/Sqrt
FP Multiply
Control Bus
Instruction Bus
Data Bus
Instruction Cache
Set A
(Lockable)
Instruction Cache
Set B
32-bit
Synchronized
System Interface
Data Cache
Set A
(Lockable)
Data Cache
Set B
The IDT logo is a trademark and RC4600, RC4650, RC3081,RC3052,RC3051,RC3041 RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
© 2008 Integrated Device Technology, Inc.
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December 5, 2008
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