IDT79RC32134 Datasheet, PDF (1/25 Pages) Integrated Device Technology – RISCore32300TM Family System Controller Chip

RISCore32300^TM Family
System Controller Chip
IDT79RC32134
Features
x _{RC32300-family System Controller}
– Direct connection between RC32364 and RC32134
– Up to 75 MHz operation
– Drives latched address bus to memory and peripherals
– Direct control of optional external data buffers
– Programmable system watch-dog timers
– Big or Little endian support
x _{Interrupt Control}
– Provides services for internal and external sources
– Allows status of each interrupt to be read and masked
x _{Three general purpose 32-bit timer/counters}
x _{Programmable IO (PIO)}
– Input/Output/Interrupt source
– Individually programmable
x _{SDRAM/EDODRAM Controller (32-bit memory only)}
– 4 banks, non-interleaved, 256 MB total
– Automatic refresh generation
x _{UART Interface}
– Two 16550 Compatible UARTs
– Baud rate support up to 1.5M
x _{8/16/32-bit boot PROM support}
x _{Boundary Scan JTAG Interface (IEEE Std. 1149.1}
compatible)
x _{Memory & Peripheral Controller}
– 6 banks, up to 8MB per bank
– 8/16/ or 32-bit interface per bank
– Supports Flash ROM, SRAM, dual-port memory, and periph-
eral devices
– Intel or Motorola style IO supports external wait-state genera-
tion
x _{4 DMA Channels}
– 4 general purpose DMA, each with Endianness swappers and
byte lane data alignment
– Any channel can be used for PCI
– Supports memory-to-memory, memory-to-I/O,memory-to-
PCI, PCI-to-PCI, I/O-to-I/O transfers, and I/O support of
scatter/gather
– Supports chaining via linked lists of records
– Supports unaligned transfers
– Supports burst transfers
– Programmable burst size
x _{PCI Bridge}
– 32-bit PCI, up to 33 MHz
– Revision 2.1 compliant
– Target and master
– Host or satellite
– Three slot PCI arbiter, on-chip
– Serial EEPROM support, for loading configuration
registers
x _{3.3V core operation}
x _{3.3V I/O operation with 5V tolerant I/O}
x _{208 pin PQFP package}
Block Diagram
Timer, UART,
Interrupt Modules
DMA Channels
RC32134
CPU I/F
PCI I/F and Bridge
EDO/SDRAM
Control
Memory I/O
Control
Data & Address bus
SDRAM/EDODRAM Control
Memory &
I/O Control
PCI Bus
The IDT logo is a registered trademark. RC64145, RC64474, RC64475, RC32134, RC4600, RC4640, RC4650, RC4700, RC3041, RC3051, RC3052, RC3081, RISController, and RISCore are trademarks of Inte-
grated Device Technology, Inc.
 2000 Integrated Device Technology, Inc.
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April 9, 2001
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