IDT79R4650 Datasheet, PDF (1/25 Pages) Integrated Device Technology – Low-Cost 64-bit RISController w/DSP Capability

Low-Cost 64-bit
RISController
w/DSP Capability
IDT79RC4650^™
)HDWXUHV
x _{High-performance embedded 64-bit microprocessor}
– 64-bit integer operations
– 64-bit registers
– 100MHz, 133MHz, 150 MHz, 180MHz, 200MHz and 267MHz
operation frequencies
x _{High-performance DSP capability}
– 133.5 Million Integer Multiply-Accumulate Operations/sec @
267 MHz
x _{High-performance microprocessor}
– 133.5 M Mul-Add/second at 267MHz
– 89 MFL0P/s at 250MHz
– >640,000 dhrystone (2.1)/sec capability at 267MHz
(352 dhrystone MIPS)
x _{High level of integration}
– 64-bit, 267 MHz integer CPU
– 8KB instruction cache; 8KB data cache
– Integer multiply unit with 133.5M Mul-Add/sec
x _{Low-power operation}
– Active power management powers-down inactive units
– Standby mode
x _{Upwardly software compatible with IDT RISController}
Family
x _{Large, efficient on-chip caches}
– Separate 8kB Instruction and 8kB Data caches
– Over 3200MB/sec bandwidth from internal caches
– 2-set associative
– Write-back and write-through support
– Cache locking to facilitate deterministic response
x _{Bus compatible with RC4000 family}
– System interface provides bandwidth up to 1000 MB/S
– Direct interface to 32-bit wide or 64-bit wide systems
– Synchronized to external reference clock for multi-master
operation
– Socket compatible with IDT RC64475 and RC64575
x _{Improved real-time support}
– Fast interrupt decode
Optional cache locking
x _{Note:“R” refers to 5V parts; “RV” refers to 3.3V parts; “RC”}
refers to both
%ORFN#'LDJUDP
352 MIPS 64-bit CPU
64-bit register file
64-bit adder
Load aligner
Store Aligner
Logic Unit
High-Perform ance
Integer Multiply
System Control Coprocessor
Address Translation/
Cache Attribute Control
Exception M anagem ent
Functions
89M FLO PS Single-Precision FPA
FP register file
P a ck /U n p a ck
FP Add/Sub/C vt/
D iv /S q r t
FP M ultiply
Control Bus
Instruction Bus
Data Bus
Instruction Cache
Set A
(Lockable)
Instruction C ache
Set B
3 2 -/6 4 -b it
S y n c h ro n ize d
System Interface
Data Cache
Set A
(Lockable)
Data Cache
Set B
The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
© 2000 Integrated Device Technology, Inc.
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March 28, 2000
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