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IDT79R3081 Datasheet, PDF (1/38 Pages) Integrated Device Technology – RISController with FPA | |||
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IDT79R3081 RISController
Integrated Device Technology, Inc.
IDT79R3081
RISControllerâ¢
with FPA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT 79R3081⢠, 79R3081E
IDT 79RV3081, 79RV3081E
FEATURES
⢠Instruction set compatible with IDT79R3000A, R3041,
R3051, and R3071 RISC CPUs
⢠High level of integration minimizes system cost
â R3000A Compatible CPU
â R3010A Compatible Floating Point Accelerator
â Optional R3000A compatible MMU
â Large Instruction Cache
â Large Data Cache
â Read/Write Buffers
⢠43VUPS at 50MHz
â 13MFlops
⢠Flexible bus interface allows simple, low cost designs
⢠Optional 1x or 2x clock input
⢠20 through 50MHz operation
⢠"V" version operates at 3.3V
⢠50MHz at 1x clock input and 1/2 bus frequency only
⢠Large on-chip caches with user configurability
â 16kB Instruction Cache, 4kB Data Cache
â Dynamically configurable to 8kB Instruction Cache,
8kB Data Cache
â Parity protection over data and tag fields
⢠Low cost 84-pin packaging
⢠Superset pin- and software-compatible with R3051, R3071
⢠Multiplexed bus interface with support for low-cost, low-
speed memory systems with a high-speed CPU
⢠On-chip 4-deep write buffer eliminates memory write stalls
⢠On-chip 4-deep read buffer supports burst or simple block
reads
⢠On-chip DMA arbiter
⢠Hardware-based Cache Coherency Support
⢠Programmable power reduction mode
⢠Bus Interface can operate at half-processor frequency
R3081 BLOCK DIAGRAM
BrCond(3:2,0)
ClkIn
Clock Generator
Unit/Clock Doubler
Master Pipeline Control
System Control
Coprocessor
(CP0)
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Int(5:0)
Translation
Lookaside Buffer
(64 entries)
Mult/Div Unit
Address Adder
PC Control
Virtual Address
FP Interrupt
Floating Point
Coprocessor
(CP1)
Register Unit
(16 x 64)
Exponent Unit
Add Unit
Divide Unit
Multiply Unit
Exception/Control
Physical Address Bus
Data Bus
32
Configurable
Instruction
Cache
(16kB/8kB)
Configurable
Data
36
Cache
(4kB/8kB)
Data Bus
Parity
Generator
4-deep
Read
Buffer
R3051 Superset Bus Interface Unit
4-deep
Write
Buffer
DMA
Arbiter
BIU
Control
Coherency
Logic
Address/
Data
DMA
Ctrl
Rd/Wr
Ctrl
SysClk Invalidate
Control
2889 drw 01
The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
5.5
5.5
SEPTEMBER 1995
DSC-9064/4
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