IDT77V1264L200 Datasheet, PDF (1/49 Pages) Integrated Device Technology – Quad Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications

Quad Port PHY (Physical Layer)
for 25.6, 51.2, and 204.8 Mbps
ATM Networks and Backplane
Applications
IDT77V1264L200
Features List
! _{Performs the PHY-Transmission Convergence (TC) and}
Physical Media Dependent (PMD) Sublayer functions for
four 204.8 Mbps ATM channels
! _{Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5}
specifications for 25.6 Mbps physical interface
! _{Operates at 25.6, 51.2, 102.4, 204.8 Mbps data rates}
! _{Individual Selection of Port Data Rates}
! _{Backwards Compatible with 77V1254L25}
! _{UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface}
! _{3-Cell Transmit and Receive FIFOs}
! _{LED Interface for status signalling}
! _{Supports UTP Category 3 and 5 physical media}
! _{Low-Power CMOS}
! _{3.3V supply with 5V tolerant inputs}
! _{144-pin PQFP Package (28 x 28 mm)}
! _{Industrial Temperature Ranges}
Description
The IDT77V1264L200 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V1264L200 implements the physical layer for
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3
and 5) to one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1264L200 also operates at 51.2 Mbps and 204.8 Mbps, and is
well suited to backplane driving applications.
The 77V1264L200-ATM layer interface is selectable as either: 16-bit
UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or quadruple 4-bit
DPI (Data Path Interface).
The IDT77V1264L200 is fabricated using IDT's state-of-the-art
CMOS technology, providing the highest levels of integration, perfor-
mance and reliability, with the low-power consumption characteristics of
CMOS.
Block Diagram
TXREF
TXCLK
TXDATA[15:0]
TXPARITY
TXSOC
TXEN
TXCLAV
TXADDR[4:0]
MODE[1:0]
RXADDR[4:0]
RXCLK
RXDATA[15:0]
RXPARITY
RXSOC
RXEN
RXCLAV
PHY-ATM
Interface
(UTOPIA or DPI)
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock Recovery
+- _{TX 0}
+- _{RX 0}
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock Recovery
+- _{Tx 1}
+- _{Rx 1}
INT
RST
RD
WR
CS
AD[7:0]
ALE
OSC
Microprocessor
Interface
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock Recovery
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
4
4
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock Recovery
RXREF
RXLED[3:0] TXLED[3:0]
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 49
 2004 Integrated Device Technology, Inc. All rights reserved. Product specification subject to change without notice.
+
- ^{TX 2}
+
- ^{RX 2}
+
- ^{TX 3}
+- _{RX 3}
3505 drw 01
.
December 2004
DSC 6029/1