IDT77305 Datasheet, PDF (1/27 Pages) Integrated Device Technology – UTOPIAFIFO 4 PORT MULTIPLEXER FIFO

UTOPIA.I.O™
4-PORT (128 X 9 X 4)
MULTIPLEXER-.I.O
1,6%%!#
.eatures
x _{Four Independent Input 128 x9 FIFO Queues}
x _{Nine bit wide input FIFOs}
x _{Single selectable 9 or 18 bit output bus}
x _{"UtopiaRx" or "UtopiaTx" Utopia compliant interface signaling}
options
x _{Separate clocks for input and output}
x _{Selectable Automatic byte insertion for 8-bit Receive Utopia to 16-}
bit Receive Utopia compliance
x _{Four 155Mbs ATM input channels can be consolidated into a}
single 622Mbs channel with no additional glue logic
x _{Maximum through put per device over 1.4Gbps}
x _{In a building block configuration multiple input channels can}
be multiplexed onto a 32, 64 or 128 bit bus.
x _{User programmable:}
– byte insert/delete, UtopiaTx/UtopiaRx mode, master/slave
configuration, byte swapping
x _{Selectable Round Robin Sequencer output control}
x _{Data clock rates to 80 MHz; access times 8.5 ns}
x _{100-pin TQPF package}
x _{Separate cell ready signals for each FIFO and cell ready}
composite signal
x _{End of cell transfer flag}
.unctional Block Diagram
CRn
CRC
ECT
CSS
RTS
BDI
RST
WCLK
ENR a
CLAVR a
SOCR a
Data a ^{(0 - 8)}
ENR b
CLAVR b
SOCR b
Data b (0 - 8)
ENR c
CLAVR c
SOCR c
Data c (0 - 8)
ENR d
CLAVR d
SOCR d
Data d (0 - 8)
©2001 Integrated Device Technology, Inc.
CELL SIZE/CELL READY
OE
ROUND
ROBIN
SEQUENCER
MSE
RRE
FIFO CONTROLLER
128 BYTES
FIFO
X 18
FIFO CONTROLLER
128 BYTES
FIFO
FIFO CONTROLLER
128 BYTES
FIFO
FIFO CONTROLLER
128 BYTES
FIFO
1
RCLK
MUX1
MUX2
LDM
SWP
XOE
ENS
CLAVS
SOCS
Q0 - Q8 ^,
Q9 - Q17
BSS
3206 drw 01
MARCH 2001
DSC-3206/3