IDT77301 Datasheet, PDF (1/29 Pages) Integrated Device Technology – UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO

UTOPIA.I.O™
1 TO 4
(128 X 9 X 4)
DEMULTIPLEXER-.I.O
1,6%%!
.eatures:
♦ _{Data transfers on fixed cell sizes}
♦ _{Programmablecellsize}
♦ _{One input port to four output ports}
♦ _{Four Independent output 128 x 9 FIFO Queues}
♦ _{Selectable eighteen bit or nine bit input bus}
♦ _{Selectable eight/nine bit or four bit output buses}
♦ _{ProgrammablechipIdentification}
♦ _{“UtopiaTx” level 2 compliant input interface signaling}
♦ _{“UtopiaTx” level 1 compliant output interface signaling}
♦ _{Separate clocks for input and output}
♦ _{Selectable In-band or Out-band routing}
♦ _{Multicastcapability}
♦ _{Data clock rates to 62.5 MHz, 10ns access time}
♦ _{Building Block Implementation allows up to 32 output channels with}
a 18, 36 or 64-bit input bus
♦ _{Four 562 Mbps output channels can be derived from a single}
1.1256 Gbps input channel with no additional glue logic
♦ _{100-pin TQPF package}
General Description
The IDT77301 UtopiaFIFO is a high-speed, low power single input
port supplying four demultiplexing FIFO output ports. Each of the four
output synchronous (clocked) FIFOs are 64 words (128 bytes) in depth.
Data is written to the input port in “cells” (fixed length data packets). The
cell size is programmable from 16 bytes to 128 bytes.
The input port can be configured to support 9-bit or 18-bit wide data
buses. (Multiple 77301’s can be configured to handle 32 and 64-bit buses
with no additional logic.)
There are four routing methods that can be used to transfer data to the
77301. Two methods use out-band routing for the port selection, which
requires use of the Address Location bus. The remaining two methods
support in-band routing, which uses the Address Location bus in conjunc-
tion with the Data bus for port selection. Utopia 2 signaling supports single
cell transfers to single output ports, but the 77301 also offers a proprietary
multicasting protocol. Multicasting enables a single cell to be transferred
simultaneously to multiple selected output ports.
The four output ports can be configured as 9-bit or 4-bit wide data
buses. (18-bit wide buses can be supported with multiple 77301’s with no
.unctional Block Diagram
RMS
MAS
BSS
ADR (0-4)
SOCR
ENR
CLAVR
Data (D0-D17)
WCLK
128 BYTE
FIFO
128 BYTE
FIFO
128 BYTE
FIFO
128 BYTE
FIFO
SOCS - a
ENS - a
CLAVS - a
Data - a (D0-D8)
SOCS - b
ENS - b
CLAVS - b
Data - b (D0-D8)
SOCS - c
ENS - c
CLAVS - c
Data - c (D0-D8)
SOCS - d
ENS - d
CLAVS - d
Data - d (D0-D8)
©2001 Integrated Device Technology, Inc.
RST
MSE
BNE
CONTROL
REGISTER
OE
1
RCLK
SLE
SCLK
SDI/P_ID0
3240 drw 01
MARCH 2001
DSC-3240/3