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IDT77252 Datasheet, PDF (1/17 Pages) Integrated Device Technology – 155 Mbps ATM SAR Controller With ABR Support for PCI-based Networking Applications
155 Mbps ATM SAR Controller
With ABR Support for PCI-based
Networking Applications
IDT77252

x Full-duplex Segmentation and Reassembly (SAR) at 155
Mbps "wire-speed" (310 Mbps aggregate speed)
x Operates with ATM Networks up to 155.52 Mbps
x Stand-alone Controller: Embedded Processor not required
x Performs ATM Layer Protocol Functions
x Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats
x Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR),
and Unassigned Bit Rate (UBR), and Available Bit Rate
(ABR) Service Classes
x Segments and Reassembles CS-PDUs into Host Memory
x Up to 16K Open Transmit Connections
x Up to 16K Simultaneous Receive Connections
x ABR, VBR, UBR Selectable per VC Time-out
x Automatic AAL5 Padding
x Four Buffer Pools for Independent or Chained Reassembly
x Supports Any Buffer Alignment Condition
x Free Buffer Queues Mapped Into PCI Memory Space
x Rx FIFO Size (Configurable to 1024 Kbytes)
x Configurable Transmit FIFO Depth for Reduced Latency
x Supports Big and Little Endian Data Transfers
x Null Cell Disable Option During Transmit
x NAND Test Mode
x RM Cell Handling
x UTOPIA Level 1 Interface to PHY
x Utility Bus Interface for PHY Management
x Serial EEPROM Interface
x EPROM Interface
x PCI 2.1 Compliant
x UNI 3.1, TM 4.0 Compliant
x Meets PCI Bus Power Management and Interface
Specification Revision 1.1
x Pin Compatible with IDT 77211 SAR
x Commercial and Industrial Temperature Ranges
x 208-Lead PQFP Package (28 x 28mm)
x Software Drivers:
– SARWIN 2 Demonstration Program
– NDIS Driver
– Vx Works (3rd party)
– Linux (3rd party)
   
The IDT77252 NICStAR™ is a member of IDT's family of products for
Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs
both the ATM Adaptation Layer (AAL) Segmentation and Reassembly
(SAR) function and the ATM layer protocol functions.
A Network Interface Card (NIC) or internetworking product based on
the ABR SAR uses host memory, rather than local memory, to reas-
semble Convergence Sublayer Protocol Data Units (CS-PDUs) from
ATM cell payloads received from the network. When transmitting, as CS-
PDUs become ready, they are queued in host memory and segmented
    
PCI BUS
16K x 32 to 512K x 32
SRAM
EPROM
32
8
33MHZ
32
IDT77252
155Mbps
PCI ATM
ABR SAR
 2001 Integrated Device Technology, Inc.
EEPROM
Rx UTOPIA Bus
8
Tx UTOPIA Bus
8
Utility Bus
8
80.0MHZ OSC.
PHY
155Mbps 2
2
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