IDT75K72234 Datasheet, PDF (1/1 Pages) Integrated Device Technology – 18M Network Search Engine (NSE) with Dual LA-1 Interface (QDR™II Interface Compliant)

18M Network Search
Engine (NSE) with
Dual LA-1 Interface
(QDR™II Interface Compliant)
Datasheet
Brief
IDT75K72234
Introduction
With the expanding Internet, all levels of the network must become
faster. This requires high-speed packet searches, which are essential
for routing, but also necessary for higher-level functions such as Quality
of Service (QoS) support and access control. To meet this need, IDT has
developed network search engines that accelerate packet processing at
OC-192 data rates and beyond.
Device Description
The 18M NSE with Dual LA-1 interface is intended to work with NPUs
having a Look Aside Interface. Multiple devices including the 18M Dual
LA-1 NSE can be connected to the same LA-1 interface. Each 18M Dual
LA-1 NSE device may be optionally point-to-point expanded up to eight
NSE devices.
NSE Features
■ _{256K x 72 (18M) Data and Mask cells}
■ _{Full Ternary Content Addressable Memory}
■ _{Supports up to 250 Million searches per second}
■ _{DynamicDatabaseManagement™}
- ConfigurableDatabasewidths
- Databases are selectable per NSE command
■ _{Programmable Power Management}
- Only the selected Database consumes power
- PowerSave logic provides additional power savings
■ _{Lookup (Search) Instructions}
- Standard Lookup
- Multi-HitLookup
- Multi-DatabaseLookup
- Re-Issue Multi-Database Lookup
- SimultaneousMulti-DatabaseLookup
■ _{Maintenance Features}
- Per entry aging support with notification
- MultiHitInvalidate
- Learn per Database
■ _{Search with learn}
- Automaticlearning
- Duplicate learn prevention per database
■ _{Multiple return index formats}
■ _{Flexible Associated Data Management}
- 0, 32, 64, or 128 bits of Associated Data per entry
■ _{Instruction Completion Notification}
■ _{Multiple contexts per interface}
■ _{Pool of 72-bit Global Mask Registers (shared across contexts)}
■ _{Parity support for interfaces and CAM core}
■ _{35mm x 35mm thermally efficient 900 BGA Package}
External Interfaces
■ _{Two independent LA-1 (QDRII compliant) interfaces}
- Frequency range from 133MHz up to 250 MHz
- Supports burst of 2 data transfers
- Echo clocks supported (CQ, CQ)
- Dynamic or programmable output impedance control
■ _{PCI2.2compliantinterface}
- OptimizedforNSEmanagement
■ _{CascadeInterface}
- 8 NSEs in a Point-to-Point Cascade
- Up to 4 Multi-Drop cascades to a single LA-1
interface
- Supports up to 32 devices per LA-1 interface
■ _{NSE attached associated SRAM glueless ZBT®Interface}
■ _{IEEE 1149.1-2001 compliant JTAG Interface}
Simplified Block Diagram
LA-1
Read
Control
Logic
LA-1
Interface
LA-1
Write
Control
Logic
1.5V
HSTL
LA-1
Read
Control
Logic
PCI Interface
3.3V TTL
CAM Core
Segment 0
Segment 1
Segment 2
LA-1
Interface
LA-1
Write
Control
Logic
Segment n-1
Segment n
JTAG Interface
2.5V LVTTL
Cascade
Interface
1.5V
HSTL
ZBT
Interface
2.5V
LVTTL
6104 drw00
MAY 2004
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. QDR™ II- Quad Data Rate _DSC-6104/03
Trademark of Cypress, IDT, Micron, NEC and Samsung). All brands or products are the trademarks or registered trademarks of their respective
owners. ZBT^® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. LA-1 refers to the approved NPF(www.npforum.org)
Look Aside Interface implementation agreement ‘Look Aside Interface LA-1.0 (www.npforum.org/techinfo/f2001.114.14a.pdf)