IDT74SSTVN16859C Datasheet, PDF (1/7 Pages) Integrated Device Technology – 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

IDT74SSTVN16859C
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
13-BIT TO 26-BIT REGISTERED IDT74SSTVN16859C
BUFFER WITH SSTL I/O
FEATURES:
• 1:2 registered output buffer
• 2.3V to 2.7V operation for PC1600, PC2100, and PC2700
• 2.5V to 2.7V operation for PC3200
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in 56 pin VFQFPN and 64 pin TSSOP packages
APPLICATIONS:
• Ideally suited for stacked DIMM DDR registered applications
• Along with CSPT857C/D, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
DESCRIPTION:
The SSTVN16859C is a 13-bit to 26-bit registered buffer designed for
2.3V-2.7V VDD for PC1600 - PC2700 and 2.5V-2.7V VDD for PC3200, and
supports low standby operation. All data inputs and outputs are SSTL_2
level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
FUNCTIONAL BLOCK DIAGRAM
RESET
51
CLK
48
49
CLK
VREF
45
D1
35
1D
C1
R
16
Q1A
32
Q1B
TO 12 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
c 2004 Integrated Device Technology, Inc.
OCTOBER 2004
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