IDT74SSTVF16857_07 Datasheet, PDF (1/6 Pages) Integrated Device Technology – 14-BIT REGISTERED BUFFER WITH SSTL I/O

IDT74SSTVF16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
14-BIT REGISTERED
BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16857
FEATURES:
• 2.3V to 2.7V Operation
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 14 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in TSSOP package
APPLICATIONS:
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
FUNCTIONAL BLOCK DIAGRAM
RESET
34
DESCRIPTION:
The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V
VDD and supports low standby operation. All data inputs and outputs are
SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
CLK
38
39
CLK
VREF
35
D1
48
1D
C1
R
1
Q1
TO 13 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
c 2003 Integrated Device Technology, Inc.
JUNE 2003
DSC-6198/8