IDT74SSTU32865 Datasheet, PDF (1/15 Pages) Integrated Device Technology – 28-BIT 1:2 REGISTERED BUFFER WITH PARITY

IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
28-BIT 1:2 REGISTERED
BUFFER WITH PARITY
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IDT74SSTU32865
FEATURES:
• 1.8V Operation
• SSTL_18 style clock and data inputs
• Differential CLK input
• Control inputs compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in 160-pin CTBGA package
APPLICATIONS:
• Along with CSPU877/A/D DDR2 PLL, provides complete solution
for DDR2 DIMMs
• Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D
DESCRIPTION:
The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed
for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with
the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2
DIMM load.
The SSTU32865 operates from a differential clock (CLK and CLK). Data
are registered at the crossing of CLK going high and CLK going low.
This device supports low-power standby operation. When the reset input
(RESET) is low, the differential input receivers are disabled, and undriven
(floating) data, clock, and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all outputs are
forced low. The LVCMOS RESET and Cx inputs must always be held at
a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has
been supplied, RESET must be held in the low state during power up.
In the DDR2 DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering reset, the
register will be cleared and the outputs will be driven low quickly, relative
to the time to disable the differential input receivers. However, when coming
out of a reset, the register will become active quickly, relative to the time to
enable the differential input receivers. As long as the data inputs are low,
and the clock is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the design of the
SSTU32865 must ensure that the outputs will remain low, thus ensuring no
glitches on the outputs.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn
outputs from changing states when both DCS0 and DCS1 are high. If either
DCS0 and DCS1 input is low, the Qn outputs will function normally. The
RESET input has priority over the DCS0 and DCS1 control and will force
the Qn outputs low and the PYTERR output high. If the DCS-control
functionality is not desired, then the CSGateEnable input can be hard-wired
to ground, in which case the set-up time requirement for DCS would be the
same as for the other D data inputs.
The SSTU32865 includes a parity checking function. The SSTU32865
accepts a parity bit from the memory controller at its input pin PARIN,
compares it with the data received on the D-inputs, and indicates whether
a parity error has occured on its open-drain PYTERR pin (active low).
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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c 2005 Integrated Device Technology, Inc.
APRIL 2005
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