IDT74LVCH16646A Datasheet, PDF (1/8 Pages) Integrated Device Technology – 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS 5 VOLT TOLERANT I/O AND BUS-HOLD

IDT74LVCH16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS
IDT74LVCH16646A
TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVCH16646A 16-bit bus transceiver and register is built using
advanced dual metal CMOS technology. This high-speed, low power
device is organized as two independent 8-bit D-type transceivers with 3-
state D-type registers.The controls circuitry is organized for multiplexed
transmission of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register features direction
control (DIR), over-riding Output Enable control (OE) and Select lines (SAB
and SBA) to select either real- time data or stored data. Separate clock inputs
are provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriate clock pins. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16646A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16646A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
56
1OE
1DIR ¹
1CLKBA ⁵⁵
54
1SBA
2
1CLKAB
3
1SAB
5
1A1
One of Eight Channels
1D
C1
1D
C1
29
2OE
2DIR
28
2CLKBA ³⁰
2SBA ³¹
27
2CLKAB
26
2SAB
52 _{1B1 2A1} ¹⁵
One of Eight Channels
1D
C1
1D
C1
42 _2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-3787/1