IDT74LVCH16501A Datasheet, PDF (1/7 Pages) Integrated Device Technology – 3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 5V TOLERANT I/O AND BUS-HOLD

IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
IDT74LVCH16501A
REGISTERED BUS TRANSCEIVER
WITH 5V TOLERANT I/O
AND BUS-HOLD
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
This 18-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power 18-bit registered bus
transceiver combines D-type latches and D-type flip-flops to allow data flow
in transparent latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable (LEAB and
LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB
is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition
of CLKAB. OEAB performs the output enable function on the B port. Data
flow from B port to A port is similar but requires using OEBA, LEBA and
CLKBA. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The LVCH16501A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16501A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB ¹
CLKBA ³⁰
LEBA ²⁸
OEBA ²⁷
CLKAB ⁵⁵
LEAB ²
3
A1
C
C
D
D
54
B1
C
C
D
D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-3688/2