IDT74LVCH16373A Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD

IDT74LVCH16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
IDT74LVCH16373A
TRANSPARENT D-TYPE
LATCH WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION
The LVCH16373A 16-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The LVCH16373A can be used for
implementing memory address latches, I/O ports, and bus drivers. The
Output Enable and Latch Enable controls are organized to operate each
device as two 8-bit latches or one 16-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
All pins of the LVCH16373A can be driven from either 3.3V or 5V devices.
This feature allows the use of the device as a translator in a mixed 3.3V/5V
supply system.
The LVCH16373A has “bus-hold” which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OE ¹
1LE ⁴⁸
1D1 ⁴⁷
D
CQ
2OE ²⁴
2LE ²⁵
2D1 ³⁶
2 _1Q1
D
CQ
13 _2Q1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2006 Integrated Device Technology, Inc.
MARCH 2006
DSC-4735/5