IDT74LVCH162245A Datasheet, PDF (1/7 Pages) Integrated Device Technology – 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD

IDT74LVCH162245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5V TOLERANT I/O
3.3V CMOS 16-BIT
BUS TRANSCEIVER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH162245A
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA (A port)
• High Output Drivers: ±24mA (B port)
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. This high-speed, low power transceiver is ideal for asynchro-
nous communication between two busses (A and B). The Direction and
Output Enable controls are designed to operate this device as either two
independent 8-bit transceivers or one 16-bit transceiver. The direction
control pin (DIR) controls the direction of data flow. The output enable pin
(OE) overrides the direction control and disables both ports. All inputs are
designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH162245A (B port) has been designed with a ±24mA output
driver. This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The LVCH162245 (A port) has series resistors in the device output
structure which will significantly reduce line noise when used with light loads.
The driver has been designed to drive ±12mA at the designated threshold
levels.
The LVCH162245A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1DIR ¹
1A1 ⁴⁷
46
1A2
1A3 ⁴⁴
1A4 ⁴³
41
1A5
40
1A6
1A7 ³⁸
1A8 ³⁷
48
1OE
2
1B1
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6
11
1B7
12
1B8
24
2DIR
2A1 ³⁶
35
2A2
33
2A3
32
2A4
30
2A5
29
2A6
27
2A7
26
2A8
25
2OE
13 _2B1
14
2B2
16
2B3
17
2B4
19 _2B5
20
2B6
22
2B7
23
2B8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4597/1