IDT74LVC823A Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

IDT74LVC823A
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
3.3V CMOS 9-BIT
BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC823A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, QSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
The LVC823A 9-bit bus-interface flip-flop is built using advanced dual
metal CMOS technology. The LVC823A device is designed specifically for
driving highly capacitive or relatively low-impedance loads. The device is
particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
With the clock-enable (CLKEN) input low, the nine D-type edge-triggered
flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN
high disables the clock buffer, latching the outputs. This device has
noninverting data (D) inputs. Taking the clear (CLR) input low causes the
nine Q outputs to go low, independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. OE does not affect internal operations of the latch. Previously stored
data can be retained or new data can be entered while the outputs are in
the high-impedance state.
The LVC823A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
FUNCTIONAL BLOCK DIAGRAM
OE ¹
CLR ¹¹
CLKEN ¹⁴
CLK ¹³
1D ²
R
C1
1D
23 _1Q
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INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
TO EIGHT OTHER CHANNELS
1
JANUARY 2004
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