IDT74LVC374A Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
IDT74LVC374A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, QSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVC374A octal edge triggered D-type flip-flop is built using advanced
dual metal CMOS technology. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads.
The LVC374A device is particularly suitable for implementing buffer regis-
ters, input-output (I/O) ports, bidirectional bus drivers, and working regis-
ters.
On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components. OE
does not affect internal operations of the latch. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
The LVC374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
FUNCTIONAL BLOCK DIAGRAM
OE ¹
CLK ¹¹
1D ³
C1
1D
2 _1Q
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
APRIL 1999
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