IDT74LVC32A Datasheet, PDF (1/5 Pages) Integrated Device Technology – 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE WITH 5 VOLT TOLERANT I/O

IDT74LVC32A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
QUADRUPLE 2-INPUT
POSITIVE-OR GATE
WITH 5 VOLT TOLERANT I/O
IDT74LVC32A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages
DESCRIPTION:
The LVC32A quadruple 2-input positive -OR gate is built using advanced
dual metal CMOS technology. The LVC32A device performs the Boolean
function Y = A + B or Y = A · B in positive logic.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVC32A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1A
1
14
VCC
A
1B
2
13
4B
Y
B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND 7
8
3Y
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
Description
xA, xB
xY
Inputs
Outputs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc.
FUNCTION TABLE (EACH GATE)⁽¹⁾
Inputs
xA
xB
H
X
X
H
L
L
Output
xY
H
H
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
OCTOBER 1999
1
DSC-4583/1