IDT74LVC16601A Datasheet, PDF (1/6 Pages) Integrated Device Technology – 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS, 5 VOLT TOLERANT I/O

IDT74LVC16601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
IDT74LVC16601A
18-BIT UNIVERSAL BUS
TRANSCEIVER WITH 3 STATE OUTPUTS,
5 VOLT TOLERANT I/O
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVC16601A 18-bit universal bus transceiver is built using advanced
dual metal CMOS technology. This 18-bit universal bus transceiver com-
bines D-type latches and D-type flip-flops to allow data flow in transparent,
latched and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/
flip-flop on the LOW-to-HIGH transition of CLKAB. Output enable OEAB is
active low. When OEAB is low, the outputs are active. When OEAB is high,
the outputs are in the high-impedance state. Data flow for B to A is similar
to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16601A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
FUNCTIONAL BLOCK DIAGRAM
OEAB ¹
CLKENAB ⁵⁶
CLKAB ⁵⁵
LEAB ²
LEBA ²⁸
CLKBA ³⁰
CLKENBA ²⁹
OEBA ²⁷
3
A1
CE
1D
C1
CLK
CE
1D
C1
CLK
54
B1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
1
JANUARY 2004
DSC-4599/3